The subject system and method are generally directed to memory controllers having measures for error detection and correction. More specifically, the subject system and method provide for a memory controller that is executable to self-actuate a writeback transaction to effect corrected storage of data in a given memory device responsive to detection of correctable error in that data as stored. Preferably, such measures are sufficiently incorporated in the memory controller that the memory controller itself may generate the writeback transaction without intervention of the particular application program or other master computer program that it serves.
Memory controllers are well known in the art. They are implemented as digital circuits dedicated to controlling/managing the flow of data written to and read from one or more memory devices, and to preserve the same by periodically refreshing the memory as needed. They may be suitably formed as separate devices or integrated with a central processing unit or other main controller, and serve the memory storage and access needs of various control or user application ‘master’ operations processed thereby. Memory controllers implement the logic necessary to read from and write to various types of memory devices, examples of which include dynamic random access memory (DRAM), as well as electrically programmable types of non-volatile memory such as flash memory, and the like.
To minimize the consequences of data corruption due to random sources of error, various error detection and correction measures are employed in the art for the storage and retrieval of data from memory devices. One example of the various known measures is the use of an Error-Correcting Code (ECC). ECC measures are widely implemented in memory controllers heretofore known in various computer applications that may be particularly vulnerable to data corruption, or more generally in high data rate or other such applications where substantial immunity to data corruption is particularly important, and the added processing burden and complexity of ECC are not prohibitive. ECC measures generally involve adding redundant ECC bits to a transmitted data segment according to a predetermined code (of selected ECC format). These ECC bits are of parity-type, and permit the data segment to be properly recovered at the receiving end (by a receiver suitably configured for the given ECC format), even if certain correctable errors were introduced in the transmission or storage of that data segment. The degree to which the errors are correctable would depend on the relevant properties of the particular code being used.
Known memory controllers suitably configured in this regard execute with sufficient autonomy to relieve the master of the processing burden to carry out routine management of data flow to and from the given memory. They also relieve the master's burden of generating the necessary transaction(s) to carry out proper recovery of corrupted data segments stored in memory with correctable error. When it comes to actually remedying the corrupted storage of data, however, known memory controllers rely on conventional scrubbing transactions, which in turn rely on the master operation's interactively providing the read-modify-write commands for appropriate writeback of data. There is therefore a need for a memory controller system capable of sufficiently autonomous operation to self-actuate the writeback transactions needed to remedy the storage of corrupted data in memory as they are encountered.